Logic Design Team Lead
Posted 14 days ago · 0 applicants
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The role in plain words
This role involves leading a team of logic designers through the complete chip development cycle from architecture to tape-out for IPU and NIC products. Day-to-day responsibilities include mentoring designers, driving design implementation using Verilog or SystemVerilog, and coordinating with cross-functional teams like backend, firmware, and software. The team lead also ensures design quality and schedule adherence.
- BSc. in Electrical Engineering or BSc. in Computer Engineering
- 7+ years chip design experience
- 3+ years design team management experience
- Proficiency in SystemVerilog/Verilog
- Strong problem-solving and communication skills
- Tools experience: LINT/CDC/RDC/SDC
- Basic knowledge with Synthesis tools
Extracted from the job description · kept up to date automatically
Who this suits
This role suits an experienced engineer with a degree in Electrical or Computer Engineering, at least 7 years of chip design experience, and 3+ years of team management experience. It is less ideal for junior designers or those seeking a remote work environment.
Full job description
Original listing · kept for referenceJob Details
Job Description:
The Ethernet Silicon Engineering Group is seeking for a talented Logic Design Team Lead to join our growing team developing state-of-the-art IPU (Infrastructure Processing Unit) and NIC (Network Internet Card) products for Data Center acceleration.
You will lead a team through full development cycle from architecture to tape-out, collaborating closely with architecture, validation, backend, firmware, software, and SOC teams.
Key Responsibilities:
• Lead and mentor a team of logic designers
• Drive design implementation from specification to silicon
• Coordinate cross-functional collaboration
• Ensure design quality and schedule adherence
Qualifications
• BSc. in Electrical Engineering or BSc. in Computer Engineering.
• 7+ years chip design experience
• 3+ years design team management experience
• Proficiency in SystemVerilog/Verilog
• Strong problem-solving and communication skills
Advantages
• Experience with Networking designs.
• Tools experience: LINT/CDC/RDC/SDC.
• Basic knowledge with Synthesis tools.
Job Type
Experienced Hire
Shift
Shift 1 (Israel)
Primary Location:
Israel, Petah-Tikva
Additional Locations:
Israel, Haifa
Business Group
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- On-site
- BSc. in Electrical Engineering or BSc. in Computer Engineering, 7+ years chip design experience, 3+ years design team management experience, Proficiency in SystemVerilog/Verilog, Strong problem-solving and communication skills