Senior Design Verification Engineer
Posted Jun 28 · 0 applicants
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The role in plain words
This role involves working on the verification of a purpose-built ASIC processor designed for analytics and AI workloads. The day-to-day responsibilities include executing verification tasks across the full chip development cycle using System Verilog and UVM methodology.
- BSc in Electronics Engineering or Computer Science
- 6+ Years of industry experience in verification, full chip dev. cycle
- Experience with System Verilog and UVM methodology
- M.Sc. in Electronics Engineering or Computer Science
- Working experience with Formal verification
- Scripting skills in Python/Perl/shell
- Hands-on experience with PCIE (Gen5 and above)
- Hands-on experience with DDR (v4 and above)
Extracted from the job description · kept up to date automatically
Who this suits
This role suits experienced engineers with at least six years of industry experience in verification and a strong background in System Verilog and UVM. It is less ideal for entry-level candidates or those without hands-on experience in full chip development cycles.
Full job description
Original listing · kept for referenceSpeedata is modernizing analytics infrastructure with the first purpose-built ASIC processor, the Analytics Processing Unit (APU), for analytics and AI data workloads. Delivering up to 100x faster Apache Spark performance while cutting infrastructure TCO by 90%, the APU executes analytics operations directly in silicon with seamless integration and no code changes.
We're looking for the best Senior Verification Engineer!
Join us and be a part of a dynamic team, which revolutionizes the parallel processor architecture.
Requirements:
• BSc in Electronics Engineering or Computer Science
• 6+ Years of industry experience in verification, full chip dev. cycle.
• Experience with System Verilog and UVM methodology - MUST
Advantages
• M.Sc. in Electronics Engineering or Computer Science
• Working experience with Formal verification
• Scripting skills in Python/Perl/shell
• Hands-on experience with two or more of the following :
• PCIE (Gen5 and above).
• DDR (v4 and above).
• AMBA protocol family, (inc. AXI4+, ACE/CHI)
• ARM core architecture.
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- BSc in Electronics Engineering or Computer Science, 6+ Years of industry experience in verification, full chip dev. cycle, Experience with System Verilog and UVM methodology