Director of Engineering
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The role in plain words
- 20+ years of proven professional experience within R&D
- Extensive leadership background managing global engineering teams across multiple countries
- Deep technical mastery across RTL Design and Design Verification (DV) flows
- Strong practical fluency with UVM methodologies and diverse automated verification frameworks
- Cadence simulation and verification toolsets
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Who this suits
Full job description
Original listing · kept for referenceAn exceptional, world-class semiconductor corporation that designs, develops, and manufactures high-performance silicon solutions and advanced microelectronics.
Their diverse product portfolio powers ultra-complex global industries, including autonomous automotive systems, heavy industrial automation, telecommunications, IoT ecosystems, security infrastructure, and next-generation smart devices.
Located in North District, offering a fully on-site, collaborative workspace alongside elite hardware engineering teams.
Position Overview-
• Director of Silicon Front-End Engineering taking global ownership over the end-to-end Front-End development lifecycle, planning, and execution of next-generation SoC projects.
• Leading, mentoring, and scaling multidisciplinary, cross-border RTL Design and Design Verification (DV) engineering teams operating across multiple countries.
• Orchestrating external resources, managing strategic vendors, and supervising subcontractors to ensure precise delivery timelines, rigorous quality standards, and product target alignment.
• Serving as the ultimate technical authority for Front-End implementation, steering methodology improvements, and driving advanced validation and simulation strategies.
Requirements-
• 20+ years of proven professional experience within the semiconductor R&D industry – Mandatory
• Extensive leadership background with a demonstrated track record managing global engineering teams across multiple countries – Mandatory
• Deep technical mastery across both RTL Design and Design Verification (DV) flows – Mandatory
• Strong practical fluency with UVM methodologies and diverse automated verification frameworks – Mandatory
• Hands-on familiarity with industry-standard simulation and verification toolsets from Cadence and Synopsys – Mandatory
• Proven experience managing subcontractors, vendors, and external development resources – Mandatory
• Exceptional communication, stakeholder management, and cross-functional leadership capabilities – Mandatory
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- 20+ years of proven professional experience within R&D, Extensive leadership background managing global engineering teams across multiple countries, Deep technical mastery across RTL Design and Design Verification (DV) flows, Strong practical fluency with UVM methodologies and diverse automated verification frameworks, Cadence simulation and verification toolsets