RTL Design Engineer, Google Cloud
Posted Jun 17 · 0 applicants
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The role in plain words
This role involves developing complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. You will define IP microarchitecture, write RTL code in Verilog or SystemVerilog, and perform quality checks like Lint and CDC. Additionally, you will collaborate with verification, power, and timing teams to optimize designs for performance, power, and area.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Verilog
- SystemVerilog
- Experience in logic design and debug with Design Verification (DV)
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience with design sign off and quality tools (Lint, CDC, VCLP etc.)
- Experience in a scripting language like Python or Perl
- Knowledge of SoC architecture and assertion-based formal verification
- Knowledge of one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family
Extracted from the job description · kept up to date automatically
Who this suits
This role suits engineers with at least four years of experience in digital logic design, RTL coding, and microarchitecture specifications. It is less ideal for those without a strong background in Verilog/SystemVerilog or experience in logic design and verification.
Full job description
Original listing · kept for referenceNote: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience in logic design and debug with Design Verification (DV).
Experience with microarchitecture and specifications.
Preferred qualifications:
Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with design sign off and quality tools (Lint, CDC, VCLP etc.).
Experience in a scripting language like Python or Perl.
Knowledge of SoC architecture and assertion-based formal verification.
Knowledge of one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family.
Knowledge of high performance and low power design techniques.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This includes creating IP Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies, including design generation automation. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. You will develop/define design options for performance, power and area.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog).
Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SoC-level.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
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Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, 4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog, Verilog, SystemVerilog, Experience in logic design and debug with Design Verification (DV)