Mixed Signal Verification Engineer
Posted May 26 · 0 applicants
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The role in plain words
This role involves developing verification strategies and creating behavioral models for analog and digital mixed-signal designs. The day-to-day work includes writing, executing, and debugging testbenches using UVM methodology and SystemVerilog, as well as running simulations from the unit level up to the top level.
- 5+ years of experience
- Experience in Behavioural Modelling (BM) of Analog design for digital verification
- Knowledge in Mixed Signals dynamic Verification using chip digital design tools
- Experience in Verilog/SystemVerilog coding
- Experience in Virtuoso Schematics tools
- Experience in UVM
- Experience in Synopsys tools
- Experience in Cadence tools
Extracted from the job description · kept up to date automatically
Who this suits
This role suits experienced verification engineers with over 5 years of experience, strong Verilog/SystemVerilog coding skills, and knowledge of behavioral modeling for analog designs. It is less ideal for entry-level engineers or those without experience in Virtuoso Schematics tools.
Full job description
Original listing · kept for referenceFor an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification engineer.
Requirements: Key Responsibilities: • Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications. • Create behavioural models for analog blocks in accordance with guidelines provided by analog designers. • Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks. • Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models. • Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs. Minimum Qualifications • 5+ years of experience • Experience in Behavioural Modelling (BM) of Analog design for digital verification • Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS] • Experience in Verilog/SystemVerilog coding • Experience in Virtuoso Schematics tools • Basic knowledge in Analog design Preferred Qualifications • Experience in UVM • Experience in both Synopsys and Cadence tools is an advantage Additional Skills • Verification Methodologies and Tools : Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. • Collaborative Environment : Ability to verify Analog/mixed-signal designs in a collaborative team environment. • Communication : Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Hybrid
- 5+ years of experience, Experience in Behavioural Modelling (BM) of Analog design for digital verification, Knowledge in Mixed Signals dynamic Verification using chip digital design tools, Experience in Verilog/SystemVerilog coding, Experience in Virtuoso Schematics tools