Senior Verification Engineer
Posted 11 days ago · 74 applicants
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The role in plain words
- At least 5 years of experience
- Ability to ramp up verification environments from scratch
- Knowledge of Verification IPs and protocols (PCIe, DDR, AXI)
- Experience with UVM, System Verilog
- Good understanding of HW/SW interaction
- Knowledge in C/C++/Python/System C
Extracted from the job description · kept up to date automatically
Who this suits
Full job description
Original listing · kept for referenceQuantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers. Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base.
The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists.
Responsibilities:
• Practicing the full range of verification aspects
• Creating a verification environment from scratch (drivers, monitors, coverage...)
• VIP (DDR/PCIe/AXI) integration
• Defining verification sequences via a complex control-flow constraint set
• System understanding of a full-stack product with strong HW-SW coupling
• Reference model integration
• Test plan definition
• Defining verification flows and creating the proper infrastructure to support it
Requirements:
• At least 5 years experience.
• Ability to ramp up verification environments from scratch
• Experience with UVM, System Verilog - Advantage
• Knowledge of Verification IPs and protocols (PCIe, DDR, AXI)
• Good understanding of HW/SW interaction- Advantage
• Knowledge in C/C++/Python/System C - Advantage
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- At least 5 years of experience, Ability to ramp up verification environments from scratch, Knowledge of Verification IPs and protocols (PCIe, DDR, AXI)