Senior Design Verification Engineer
Posted 6 days ago · 0 applicants
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The role in plain words
- 7+ years of experience as a verification engineer
- Proficient in SystemVerilog
- Proficient in UVM methodology
- Strong debugging and problem-solving skills
Extracted from the job description · kept up to date automatically
Who this suits
Full job description
Original listing · kept for referenceResponsibilities:
• Develop and execute verification plans for digital designs.
• Create and implement testbenches using SystemVerilog and UVM methodology.
• Perform functional verification, simulation, and formal verification to identify and resolve design issues.
• Collaborate with hardware, software, and firmware teams for comprehensive verification coverage.
Requirements:
• 7+ years of experience as a verification engineer.
• Proficient in SystemVerilog and UVM methodology – MUST.
• Strong debugging and problem-solving skills.
Location: Jerusalem or Petah Tikva.
Job number: 1870.
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- 7+ years of experience as a verification engineer, Proficient in SystemVerilog, Proficient in UVM methodology, Strong debugging and problem-solving skills