Senior FPGA Engineer
Posted 28 days ago · 0 applicants
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The role in plain words
- Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering (or equivalent)
- 3-5 Years of experience with FPGA design flow including synthesis, place & route and static timing analysis
- Strong proficiency in RTL design and verification (Verilog/VHDL)
- Solid understanding of digital design, timing analysis, clocking architectures, and CDC techniques
- Strong knowledge of XILINX design flow (VIVADO)
- Experience in Xilinx SoC architecture, memory/processor subsystems, and interconnect experience
- Python / C/C++ / MATLAB
Extracted from the job description · kept up to date automatically
Who this suits
Full job description
Original listing · kept for referenceAbout Us
KayHut is a young, innovative, fast-growing company in the cyber research & security domain. We do what no one else does – and have great fun doing it.
We’re looking for a highly skilled and motivated FPGA Engineer to join our Simulation & Algorithm team.
What You’ll Do
• Define FPGA requirements and participate in system-level architecture decisions.
• Design and validate RTL using System Verilog.
• Develop real-time, multi-clock algorithms.
• Run FPGA design flow including synthesis, place & route and static timing analysis.
• Integrate FPGA logic with embedded processors, memory interfaces, and high-speed I/Os.
• Perform bring-up, debugging, and optimization using logic analyzers, oscilloscopes, and FPGA toolchains.
• Maintain and improve existing FPGA IP blocks and documentation.
• Collaborate with multidisciplinary engineering teams and participate in design reviews.
Requirements
• Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering (or equivalent).
• 3-5 Years of experience with FPGA design flow including synthesis, place & route and static timing analysis.
• Strong proficiency in RTL design and verification (Verilog/VHDL).
• Solid understanding of digital design, timing analysis, clocking architectures, and CDC techniques.
• Strong knowledge of XILINX design flow (VIVADO).
• Experience with design methodologies targeted to achieve specified frequency or area targets.
• Strong analytical and problem-solving skills, with the ability to work in cross-functional engineering team.
Nice to Have
• Experience in Xilinx SoC architecture, memory/processor subsystems, and interconnect experience.
• Python / C/C++ / MATLAB
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering (or equivalent), 3-5 Years of experience with FPGA design flow including synthesis, place & route and static timing analysis, Strong proficiency in RTL design and verification (Verilog/VHDL), Solid understanding of digital design, timing analysis, clocking architectures, and CDC techniques, Strong knowledge of XILINX design flow (VIVADO)