CAD Engineer - Static Timing Analysis & Physical Design
Posted Jun 22 · 0 applicants
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The role in plain words
This role involves developing and supporting advanced Static Timing Analysis (STA) flows and methodologies for physical design infrastructure. You will write Python-based tools for timing analysis, constraint validation, and ECO automation, while collaborating with design teams to debug timing violations. Additionally, you will interface with EDA vendors and support multiple projects during critical tapeout phases.
- Proven experience with PrimeTime for timing analysis, constraint development, and signoff
- Deep understanding of timing concepts: setup/hold analysis, clock domain crossing, multicycle paths, false paths, and timing exceptions
- Experience with advanced timing concepts: OCV, statistical timing analysis, margins and variation analysis
- Solid understanding of RTL-to-GDSII flow with focus on timing-critical stages
- Knowledge of power-aware timing analysis and low-power design methodologies
- BS/MS in Electrical Engineering, Computer Engineering, or Computer Science
- Demonstrated track record of successful timing closure on complex designs
- Proficient in SQL with hands-on experience in MySQL and PostgreSQL for timing data management and analysis
Extracted from the job description · kept up to date automatically
Who this suits
This role suits engineers with proven experience in PrimeTime, a deep understanding of timing concepts like setup/hold and clock domain crossing, and expert-level Python programming skills. It is less ideal for those without a solid understanding of the RTL-to-GDSII flow or experience in advanced timing concepts like OCV and statistical timing analysis.
Full job description
Original listing · kept for referenceSummary As a member of our PD CAD team reporting to the STA manager, you will develop and support advanced Static Timing Analysis flows and methodologies while contributing to the broader Physical Design infrastructure. This role combines deep STA expertise with modern software engineering practices to deliver robust, scalable timing closure solutions for cutting-edge silicon designs. You will work closely with Physical Design teams, methodology teams, and EDA vendors to ensure timing signoff success across multiple advanced technology nodes.
Description You will drive timing methodology development and support timing closure across multiple concurrent projects. Your work will span from flow automation and database-driven analysis to direct collaboration with design teams during critical tapeout phases.
Responsibilities
• Develop and maintain automated STA flows, from constraint generation through signoff reporting
• Build and optimize timing databases for cross-project analysis and historical trending
• Create Python-based tools for timing analysis, constraint validation, and ECO automation
• Collaborate with design teams to debug timing violations and develop closure strategies
• Interface with EDA vendors on tool bring-up, validation, and advanced feature adoption
• Support multiple projects simultaneously during timing closure and tapeout phases
Minimum Qualifications
• Proven experience with PrimeTime for timing analysis, constraint development, and signoff
• Deep understanding of timing concepts: setup/hold analysis, clock domain crossing, multicycle paths, false paths, and timing exceptions
• Experience with advanced timing concepts: OCV, statistical timing analysis, margins and variation analysis
• Solid understanding of RTL-to-GDSII flow with focus on timing-critical stages
• Knowledge of power-aware timing analysis and low-power design methodologies
• Expert-level Python programming for automation, data analysis, and tool integration
Preferred Qualifications
• BS/MS in Electrical Engineering, Computer Engineering, or Computer Science
• Demonstrated track record of successful timing closure on complex designs
• Proficient in SQL with hands-on experience in MySQL and PostgreSQL for timing data management and analysis
• This role offers the opportunity to shape next-generation timing methodologies while working with cutting-edge technologies and talented engineering teams across HWTech.
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Role Number: 200666036-1451
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Proven experience with PrimeTime for timing analysis, constraint development, and signoff, Deep understanding of timing concepts: setup/hold analysis, clock domain crossing, multicycle paths, false paths, and timing exceptions, Experience with advanced timing concepts: OCV, statistical timing analysis, margins and variation analysis, Solid understanding of RTL-to-GDSII flow with focus on timing-critical stages, Knowledge of power-aware timing analysis and low-power design methodologies