Senior BackEnd (Physical design) Engineer
Posted 29 days ago · 0 applicants
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The role in plain words
This role involves taking ownership of the full RTL-to-GDSII physical design flow, working on complex high-frequency and low-power backend implementation. Day-to-day responsibilities include floorplanning, timing closure, power analysis, physical verification, and scripting to improve CAD flows. The engineer will also collaborate closely with design teams and external vendors to ensure first-pass silicon success.
- 10+ years in backend design experience
- Strong expertise of full RTL2GDSII
- Logic synthesis & equivalence checking
- Constraints definition and writing
- Complicated IP integration
- Experience in Synopsys/Cadence tools
Extracted from the job description · kept up to date automatically
Who this suits
This role suits experienced backend engineers with at least 10 years of experience in physical design and full RTL2GDSII flows. It is less ideal for junior engineers or those looking for a purely front-end RTL design position.
Full job description
Original listing · kept for referenceFor an exciting well-funded start-up, we are looking for a Backend Team member.
You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors.
Requirements:
Key responsibilities:
• RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success.
• Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static
Timing Analysis (STA), timing eco implementation.
• Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced
clocking (CTS/Clock-Mesh) and Hierarchical Design flows.
• Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets.
• Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop
analysis.
• IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools.
• Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team.
• CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows.
Minimum Qualifications
• Experience of 10+ years in backend design
• Strong expertise of full RTL2GDSII including:
• Logic synthesis & equivalence checking
• Constraints definition and writing
• Complicated IP integration
• Memory compilers and other automated block generators
• DFT
• Floorplanning, PG Mesh
• P&R
• Low power design including definition, implementation and verification
• Timing STA
• IR-Drop
• BS/MS in EE/CE from lead universities
Preferred Qualifications
• Team player
• Highly motivated
• Learning abilities
• Good communication
• Work with external vendors
• Experience in Synopsys/Cadence tools is an advantage
• Low power techniques
• Clock-mesh/ multi source cts
• Hierarchical design flow
• Experience in tape-out procedures
• RTL code reading
A very interesting job and good conditions are guaranteed to the candidates
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- 10+ years in backend design experience, Strong expertise of full RTL2GDSII, Logic synthesis & equivalence checking, Constraints definition and writing, Complicated IP integration