SRAM Design Lead / Architect

Summary

We're looking for a principal-level SRAM design lead to architect and drive custom embedded memory development on our most advanced process node, from specification through tapeout. You'll own the technical roadmap for our SRAM instances, set architecture decisions that balance area, power, speed, and yield under aggressive variation and leakage constraints, and lead a team of circuit, layout, and verification engineers through the full design cycle.

Responsibilities

• Define SRAM architecture: bitcell selection, array organization, redundancy scheme, and target PPA specs under advanced-node variation and leakage constraints

• Make key trade-off calls between density, speed, power, and yield at the leading edge of the process roadmap

• Coordinate across circuit design, layout, verification, and DFT to keep the project on schedule despite the added complexity of a bleeding-edge node

• Own the memory compiler or hard-macro generation strategy if instances need to be configurable

• Interface directly with foundry PDK and DTCO teams on process-specific constraints, including early-silicon or pre-production PDKs

• Review and sign off on critical design decisions, corner cases, and tapeout readiness

• Set the technical bar for the team and mentor senior engineers navigating a new node for the first time

Required qualifications

• 15+ years in analog/mixed-signal or memory circuit design, with direct SRAM tapeout experience across multiple process generations

• Hands-on experience designing SRAM at or near the leading edge (advanced FinFET or GAA/nanosheet nodes)

• Deep understanding of bitcell physics, sense amp design, and SRAM failure modes under high process variation and low-voltage operation

• Track record of taking multiple custom memory designs from spec to silicon, including at least one on a bleeding-edge node

• Strong grasp of yield/Monte Carlo analysis under advanced-node variation, and how it drives design margin decisions

• Experience working directly with foundry PDKs, including engagement during early or pre-production PDK phases

Preferred qualifications

• Experience with GAA/nanosheet transistor architectures specifically, not just FinFET

• Direct collaboration history with foundry DTCO (design-technology co-optimization) teams

• Prior people-management or technical-lead experience

• Familiarity with memory compiler architectures (Synopsys, Cadence, or in-house)