Senior Design Engineer
Posted Jun 27 · 0 applicants
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The role in plain words
This role involves taking ownership of key digital blocks for next-generation network switches, leading the design process from architecture definition through implementation. You will drive block design tasks including area and timing optimization, lint, and CDC/RDC analysis, while collaborating closely with verification engineers.
- Electrical Engineering B.Sc / M.Sc University degree
- 5+ years of relevant experience in digital design
- Proficient in RTL design using Verilog or SystemVerilog
- Experience with linting, CDC/RDC, synthesis, timing closure, power optimization, and backend flows
- Strong problem-solving and analytical skills
- Verification experience using SystemVerilog and UVM
Extracted from the job description · kept up to date automatically
Who this suits
This role suits experienced digital design engineers with a degree in Electrical Engineering and at least 5 years of experience in RTL design using Verilog or SystemVerilog. It is less ideal for entry-level engineers or those without experience in synthesis, timing closure, and backend flows.
Full job description
Original listing · kept for referenceAbout Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
We are a highly skilled development team of talented engineers, driving the development of Marvell's next-generation network switches.
Our team is responsible for a wide range of IPs for switching products, from initial definition through architecture, design, and verification.
What You Can Expect
• Take ownership of one or more key digital blocks, leading the design from architecture definition through implementation.
• Drive all aspects of block design, including area and timing optimization, lint, and CDC/RDC analysis
• Work closely with the verification engineers to support and contribute to block-level verification, ensuring alignment between design and verification goals
What We're Looking For
• Electrical Engineering B.Sc / M.Sc University degree
• 5+ years of relevant experience in digital design
• Proficient in RTL design using Verilog or SystemVerilog
• Experience with linting, CDC/RDC, synthesis, timing closure, power optimization, and backend flows
• Verification experience using SystemVerilog and UVM – an advantage
• Strong problem-solving and analytical skills
• Quick learner with the ability to understand complex systems
• Effective team player with excellent collaboration and communication skills
Additional Compensation And Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Electrical Engineering B.Sc / M.Sc University degree, 5+ years of relevant experience in digital design, Proficient in RTL design using Verilog or SystemVerilog, Experience with linting, CDC/RDC, synthesis, timing closure, power optimization, and backend flows, Strong problem-solving and analytical skills