Physical Design Backend Engineer
Posted 29 days ago · 0 applicants
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The role in plain words
This role involves physical design chip development from RTL to GDS for high-speed networking silicon devices. Day-to-day work includes handling block-level synthesis, place and route, timing closure, power distribution, and physical verification to optimize for power, area, and performance. Engineers will also work on flow development and resolve complex timing and congestion issues.
- B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience
- 2+ years of experience
- Deep understanding of all aspects of Physical construction and Integration
- Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)
- Great teammate
- Proven experience in RTL2GDS flows and methodologies
- Knowledge in physical design flows and methodologies (PNR, STA, physical verification)
Extracted from the job description · kept up to date automatically
Who this suits
This role suits electrical or computer engineers with at least two years of experience in physical design construction and integration. It is less ideal for candidates lacking familiarity with standard EDA tools like Synopsys or Cadence or those without an engineering degree background.
Full job description
Original listing · kept for referenceNVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What You'll Be Doing
• Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
• Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
• Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
• Taking part inflows development.
What We Need To See
• B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience.
• 2+ years of experience.
• Proven experience in RTL2GDS flows and methodologies. (advantage)
• Knowledge in physical design flows and methodologies (PNR, STA, physical verification). (advantage)
• Deep understanding of all aspects of Physical construction and Integration.
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
• Great teammate.
NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!
, , JR2010808
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience, 2+ years of experience, Deep understanding of all aspects of Physical construction and Integration, Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.), Great teammate