Verification Team Lead

Design Verification Team Lead

A leading global semiconductor company is looking for an experienced Design Verification Lead to join a highly technical R&D team developing next-generation ASIC and SoC technologies.

This is an opportunity to combine technical leadership with hands-on engineering, leading verification activities while remaining deeply involved in architecture, methodology, and debugging.

In this role you will:

• Define verification strategies and test plans for complex IPs and subsystems.

• Develop and maintain advanced UVM/SystemVerilog verification environments.

• Lead and mentor a small Design Verification team.

• Drive debug activities across RTL, verification environments, and system-level integration.

• Collaborate closely with Design, Architecture, Validation, and Emulation teams.

• Influence verification methodology and quality across the organization.

We're looking for:

• 7+ years of Design Verification experience.

• Strong expertise in UVM and SystemVerilog.

• Experience with constrained-random and coverage-driven verification.

• Strong understanding of ASIC/SoC architecture.

• Experience leading projects, mentoring engineers, or driving technical initiatives.

• Scripting experience (Python, Perl, Tcl, or Shell).

Nice to have:

• Experience with high-speed interfaces (PCIe, USB, Display, SerDes).

• Knowledge of low-power design, reset and clock-domain verification.

• Experience with regression management and verification sign-off.

Location: Haifa (On-site, 5 days per week)

If you're looking for an opportunity to work on cutting-edge silicon, influence verification methodology, and grow in a technically strong environment, I'd be happy to share more details.