Verification Engineer
Posted 24 days ago · 0 applicants
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The role in plain words
- B.Sc. in EE/CE (or related)
- 3+ years of verification experience
- Strong SystemVerilog/UVM
- experience with Verdi/Questa/VCS
- Proven self-learning, flexibility, and ownership of undefined work
- Protocols: AMBA/AXI/AHB, PCIe, Ethernet
- Scripting: Python, Perl, Tcl
- Tools: Git, Jira
Extracted from the job description · kept up to date automatically
Who this suits
Full job description
Original listing · kept for referenceabra R&D is seeking for a Verification Engineer. We are looking for an Adaptable Verification Engineer who can move across blocks and tasks, partner with design/FPGA/architecture, and own floating assignments with partial specs. Key Responsibilities: • Build/maintain SystemVerilog/UVM environments; write testbenches, simulations, and regressions. • Analyze specs- create verification plans; drive debug and bug fixing to closure. • Track functional/code coverage; document flows and improve team productivity. • Context‑switch across blocks; support integration and ad‑hoc scripting/automation.
Requirements: • B.Sc. in EE/CE (or related). • 3+ years of verification experience in ASIC/SoC. • Strong SystemVerilog/UVM; experience with Verdi/Questa/VCS. • Proven self‑learning, flexibility, and ownership of undefined work; clear teamwork/communication. Nice to Have • Protocols: AMBA/AXI/AHB, PCIe, Ethernet. • Scripting: Python, Perl, Tcl. • Tools: Git, Jira.
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Hybrid
- B.Sc. in EE/CE (or related), 3+ years of verification experience, Strong SystemVerilog/UVM, experience with Verdi/Questa/VCS, Proven self-learning, flexibility, and ownership of undefined work