Senior Verification Engineer
Posted Jun 18 · 0 applicants
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The role in plain words
This role involves taking end-to-end ownership of block and cluster verification from scratch for high-speed communication technology. The day-to-day work includes building verification environments using SystemVerilog and UVM, defining test plans, and writing coverage measures for corner cases. You will also collaborate closely with design, architecture, and algorithm teams to debug functionality and close verification metrics.
- 10+ years of experience
- Performed at least 2 or more full block/system verification cycles
- In depth knowledge in VLSI verification flow, languages and concepts
- Verification using one of the known methodologies (eRM, UVM, OVM)
- Build verification environments using SystemVerilog
- Experience in data path or data protocols, specifically Ethernet
Extracted from the job description · kept up to date automatically
Who this suits
This role suits experienced verification professionals with over 10 years of experience and a deep knowledge of VLSI verification flows and UVM. It is less ideal for those without experience in full block or system verification cycles or those looking for a junior-level position.
Full job description
Original listing · kept for referenceFor an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.
Requirements: Key responsibilities: • Ownership of block\cluster verification end to end from scratch. • Lead efforts of test bench architecture, Vplan definition and functional coverage. • Work closely with the design, architecture, algo teams and other stakeholders. • Support other team members and mentor less experienced engineers. Requirements • 10+ years of experience – a must • Performed at last 2 or more full block/system verification cycles. • In depth knowledge in VLSI verification flow, languages and concepts. • Experience in data path or data protocols, specifically Ethernet - preferred • Verification using one of the known methodologies (eRM, UVM, OVM). Responsibilities • Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers. • Build verification environments using SystemVerilog and UVM. • Identify and write all types of coverage measures for corner-cases. • Debug the functionality with design engineers. • Perform coverage collection and follow the metrices to close the full functionality.
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Hybrid
- 10+ years of experience, Performed at least 2 or more full block/system verification cycles, In depth knowledge in VLSI verification flow, languages and concepts, Verification using one of the known methodologies (eRM, UVM, OVM), Build verification environments using SystemVerilog