Software Engineering Manager
Posted Jun 17 · 0 applicants
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The role in plain words
- Leading schematic capture and component selection for high-density, multi-layer (20+ layers) PCBs integrating high-power ASICs and high-speed memory
- Designing and validating critical high-speed interfaces, including PCIe Gen 5, DDR5, and LPDDR5
- Leading and mentoring specialized Signal Integrity (SI) engineers
- Serving as the central technical link between Silicon (ASIC) teams, Power, Mechanics, PCB Layout, and Manufacturing
- Leading the lab bring-up of "first silicon" and initial boards, performing deep-dive debugging of complex hardware issues across hardware, firmware, and software layers
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Who this suits
Full job description
Original listing · kept for referenceA disruptive Semiconductor startup specializing in hardware acceleration for Big Data Analytics. The company’s core innovation is a custom-built ASIC (APU) designed to eliminate bottlenecks in data center processing, enabling unprecedented analytical speeds.
Backed by industry-leading investors, the company is currently scaling its R&D to deliver the next generation of APU accelerator boards.
The company is based in a central tech hub with excellent transit accessibility and offers a high-end engineering environment with a flexible hybrid work model (1 day WFH).
Responsibilities-
Board Design Leadership: Leading schematic capture and component selection for high-density, multi-layer (20+ layers) PCBs integrating high-power ASICs and high-speed memory.
High-Speed Interface Design: Designing and validating critical high-speed interfaces, including PCIe Gen 5, DDR5, and LPDDR5.
Technical Management: Leading and mentoring specialized Signal Integrity (SI) engineers to ensure rigorous standards in power delivery, thermal management, and SI.
Cross-Functional Orchestration: Serving as the central technical link between Silicon (ASIC) teams, Power, Mechanics, PCB Layout, and Manufacturing.
Lab & Bring-up Ownership: Leading the lab bring-up of "first silicon" and initial boards, performing deep-dive debugging of complex hardware issues across hardware, firmware, and software layers.
Standards Enforcement: Ensuring design compliance with stringent signal integrity (crosstalk, impedance matching, insertion loss) and power delivery requirements.
Requirements-
B.Sc. in Electrical Engineering or Electronics – Mandatory.
6 years of experience as a Board Design Engineer, specifically focused on schematics and layout supervision for servers, networking, or HPC products – Mandatory.
Proven experience in designing with Serial Interfaces (SerDes, PCIe, Ethernet, DDR) and a deep understanding of Signal Integrity principles – Mandatory.
EDA Proficiency: Expert-level mastery of EDA tools (e.g., Cadence Concept/Allegro or similar) – Mandatory.
Extensive hands-on experience in lab bring-up and debugging complex SoC-based systems.
System-Level Troubleshooting: Demonstrated ability to identify and resolve multifaceted hardware, component, and assembly issues.
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Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Leading schematic capture and component selection for high-density, multi-layer (20+ layers) PCBs integrating high-power ASICs and high-speed memory, Designing and validating critical high-speed interfaces, including PCIe Gen 5, DDR5, and LPDDR5, Leading and mentoring specialized Signal Integrity (SI) engineers, Serving as the central technical link between Silicon (ASIC) teams, Power, Mechanics, PCB Layout, and Manufacturing, Leading the lab bring-up of "first silicon" and initial boards, performing deep-dive debugging of complex hardware issues across hardware, firmware, and software layers