Verification Specialist
Posted 24 days ago · 0 applicants
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The role in plain words
This role involves designing and developing a new FPGA verification environment from the ground up for defense products. The daily responsibilities include building verification environments using SystemVerilog and UVM, creating test plans, executing simulations, and developing automation tools with Python and TCL.
- B.Sc. in Electrical/Electronics Engineering
- 3+ years of FPGA/ASIC Verification experience
- SystemVerilog
- UVM
- Verification environment integration and coverage analysis
- Assertion Based Verification (ABV)
- Experience with Verification IPs
- Familiarity with PCIe, Ethernet, I2C, SPI, AXI
- RTL design background (Verilog/VHDL)
Extracted from the job description · kept up to date automatically
Who this suits
This role suits experienced engineers with a B.Sc. in Electrical or Electronics Engineering and at least 3 years of FPGA/ASIC verification experience, particularly those skilled in SystemVerilog and UVM. It is less ideal for entry-level candidates or those without hands-on experience in verification methodologies and scripting.
Full job description
Original listing · kept for referenceA leading defense company in Central Israel is rebuilding its FPGA verification infrastructure and is looking for an experienced FPGA Verification Engineer to take part in designing and developing a new verification environment from the ground up for cutting-edge defense products.
This is a great opportunity to influence verification methodologies, work on complex FPGA-based systems, and collaborate with multidisciplinary engineering teams developing next-generation technologies.
What you'll do:
• Build and develop advanced verification environments using SystemVerilog & UVM
• Create test plans, testbenches and execute simulations
• Develop Functional Coverage, Constraint Random testing, Scoreboards and Register Models
• Support and improve existing Verilog/VHDL environments
• Develop automation tools using Python & TCL
We're looking for:
• B.Sc. in Electrical/Electronics Engineering
• 3+ years of FPGA/ASIC Verification experience
• Strong hands-on experience with SystemVerilog & UVM
• Experience with verification environment integration and coverage analysis
• Python and TCL scripting skills
Nice to have:
• Assertion Based Verification (ABV)
• Experience with Verification IPs
• Familiarity with PCIe, Ethernet, I2C, SPI, AXI
• RTL design background (Verilog/VHDL)
If you're looking for a role where you can build, influence and make a real technical impact rather than just maintain existing environments, I'd love to hear from you!
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- B.Sc. in Electrical/Electronics Engineering, 3+ years of FPGA/ASIC Verification experience, SystemVerilog, UVM, Verification environment integration and coverage analysis