VLSI Design Engineer
Posted Mar 6 · 0 applicants
Saving, applying or scoring takes a few seconds to set up your free account.
The role in plain words
This role involves designing sophisticated communication systems from scratch as a VLSI Design Engineer or Micro-architect. The daily responsibilities include finding creative solutions to architectural challenges and handling the fine details of implementation.
- 5 years of experience as ASIC/FPGA designer
- Strong Verilog/System-Verilog experience
- Familiar with simulation tools/environments, verification methodologies
- Strong team player, solid interpersonal skills
- Entrepreneurial can-do attitude, self-motivated, able to work independently
- Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
- Design DSP of oriented blocks
- Ethernet (100G and above)
- Scripting experience using several of the following: Python, Perl, TCL
Extracted from the job description · kept up to date automatically
Who this suits
This role suits experienced ASIC or FPGA designers with at least 5 years of experience and strong Verilog or System-Verilog skills. It is less ideal for entry-level engineers or those without a background in electrical or computer engineering.
Full job description
Original listing · kept for referenceWe are looking for talented and experienced VLIS Design Engineers/Micro-architects. As an VLIS Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch. In this position you will be responsible for coming up with creative solutions to architectural challenges and crafting the very fine details of the implementation
Requirements: Job requirements: 5 years of experience as ASIC/FPGA designer Strong Verilog/System-Verilog experience Familiar with simulation tools/environments, verification methodologies Strong team player, solid interpersonal skills Entrepreneurial can-do attitude, self-motivated, able to work independently BS/MS in EE/CE from lead universities Background in one or more of the following domains is an advantage: Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT) Design DSP of oriented blocks Ethernet (100G and above) Scripting experience using several of the following: Python, Perl, TCL
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Hybrid
- 5 years of experience as ASIC/FPGA designer, Strong Verilog/System-Verilog experience, Familiar with simulation tools/environments, verification methodologies, Strong team player, solid interpersonal skills, Entrepreneurial can-do attitude, self-motivated, able to work independently