BackEnd (Physical design) Engineer
Posted 29 days ago · 0 applicants
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The role in plain words
This role involves taking semiconductor designs from RTL to GDSII, managing floorplanning, power grids, synthesis, and place and route tasks. You will work on timing closure, advanced low-power implementation, physical verification, and script automation to support CAD flows. Additionally, you will collaborate closely with design and DFT teams to integrate complex IPs and manage tape-out procedures.
- 5+ years of experience in backend design
- Strong expertise of full RTL2GDSII flow (Logic synthesis, equivalence checking, constraints definition, IP integration, memory compilers, DFT, Floorplanning, PG Mesh, P&R, Low power design, Timing STA, IR-Drop)
- BS/MS in EE/CE from lead universities
- Experience in Synopsys/Cadence tools
- Experience in tape-out procedures
- RTL code reading
Extracted from the job description · kept up to date automatically
Who this suits
This role suits experienced backend physical design engineers with at least 5 years of experience in full RTL2GDSII flows and a degree in Electrical or Computer Engineering. It is less ideal for junior candidates or those without extensive hands-on experience in timing closure and low-power implementation.
Full job description
Original listing · kept for referenceFor an exciting well-funded start-up, we are looking for a Backend Team member.
You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors.
Requirements:
Key responsibilities:
• RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success.
• Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static
Timing Analysis (STA), timing eco implementation.
• Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced
clocking (CTS/Clock-Mesh) and Hierarchical Design flows.
• Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets.
• Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop
analysis.
• IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools.
• Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team.
• CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows.
Minimum Qualifications
• Experience of 5+ years in backend design
• Strong expertise of full RTL2GDSII including:
• Logic synthesis & equivalence checking
• Constraints definition and writing
• Complicated IP integration
• Memory compilers and other automated block generators
• DFT
• Floorplanning, PG Mesh
• P&R
• Low power design including definition, implementation and verification
• Timing STA
• IR-Drop
• BS/MS in EE/CE from lead universities
Preferred Qualifications
• Team player
• Highly motivated
• Learning abilities
• Good communication
• Work with external vendors
• Experience in Synopsys/Cadence tools is an advantage
• Low power techniques
• Clock-mesh/ multi source cts
• Hierarchical design flow
• Experience in tape-out procedures
• RTL code reading
A very interesting job and good conditions are guaranteed to the candidates
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- 5+ years of experience in backend design, Strong expertise of full RTL2GDSII flow (Logic synthesis, equivalence checking, constraints definition, IP integration, memory compilers, DFT, Floorplanning, PG Mesh, P&R, Low power design, Timing STA, IR-Drop), BS/MS in EE/CE from lead universities