Senior Design Verification Engineer
Posted 20 days ago · 0 applicants
Saving, applying or scoring takes a few seconds to set up your free account.
The role in plain words
This role involves architecting, deploying, and maintaining advanced pre-silicon test benches and automated verification flows using UVM methodology. You will build verification infrastructure, integrate C++ reference models, and work closely with design and integration teams to identify and resolve hardware anomalies. Additionally, you will develop internal tools and scripting infrastructure for continuous integration and regression flows.
- Engineering degree
- 10+ years of hands-on experience in ASIC verification using UVM System Verilog
- Experience on methodologies such as UVM, constrained-Random Verification and Assertion Based Verification (ABV)
- Experience in using modern EDA Tools Suites: Front-end IC simulation and verification tools (Questa, Xcelium)
- Experience in unit-level as well as subsystem/full-chip verification
- Good knowledge of C/C++
Extracted from the job description · kept up to date automatically
Who this suits
This role suits experienced engineers with over 10 years of hands-on experience in ASIC verification using UVM System Verilog and strong proficiency in automation scripting. It is less ideal for junior engineers or those without extensive experience in complex ASIC or SoC designs.
Full job description
Original listing · kept for referenceThe Design Verification Engineer is responsible for architecting, deploying, and maintaining advanced pre-silicon test benches, reference models, and automated verification flows to achieve sign-off quality using UVM methodology.
In this role, you will build the UVM verification infrastructure and work closely with chip architects, RTL/VLSI design, Design, and Platform Integration (PI) teams within an advanced development environment, leveraging state-of-the-art development and verification tools to identify, debug, and support the resolution of complex hardware anomalies.
RESPONSIBILITIES
As a Design Verification Engineer, you will be responsible for different HW blocks at module-level and sub-system level. You will contribute across a range of technical areas, playing a key role in ensuring high-quality, scalable, and efficient verification solutions.
• UVM environment architecture: Design build, Optimize and maintain scalable and reusable UVM environment.
• Reference model integration: Integrate and support high level bit accurate reference models in C++ to serve as golden reference in UVM environment.
• Modern verification techniques: Deploy advanced methodologies including Assertion-based verification (SVA), Functional driven verification (CDV), and formal property checking to maximize efficiency.
• Automation & Tool creation: Develop internal tools, advanced scripting infrastructure and continuous integration (CI/CD), regressions flows (Gitlab CI).
• Driving the team’s verification efforts.
• Methodology & Sign-off: Review verification plans and establish infrastructure metrics (functional coverage, code coverage and formal proofs) to drive verification closure.
REQUIRED EXPERIENCE & KNOWLEDGE
• Engineering degree with 10+ years of hands-on experience in ASIC verification using UVM System Verilog
• Experience on methodologies such as UVM, constrained-Random Verification and Assertion Based Verification (ABV).
• Experience in using modern EDA Tools Suites: Front-end IC simulation and verification tools (Questa, Xcelium).
• Experience in unit-level as well as subsystem/full-chip verification.
• Experience working on complex ASIC or SOC designs
• Experience in Infrastructure Automation with strong proficiency in Python, SCons, MakeFile, git for automated flow generation, regression management and data parsing.
• Good knowledge of C/C++ is a plus
• System-Level understanding
• Experience with SOCs in the communications field – advantage
Questions about this role
- This listing did not state a salary. We only show pay when the employer publishes it.
- Engineering degree, 10+ years of hands-on experience in ASIC verification using UVM System Verilog, Experience on methodologies such as UVM, constrained-Random Verification and Assertion Based Verification (ABV), Experience in using modern EDA Tools Suites: Front-end IC simulation and verification tools (Questa, Xcelium), Experience in unit-level as well as subsystem/full-chip verification