VLSI Engineer
פורסם 28 ביוני · 0 מועמדים
התפקיד במילים פשוטות
מהנדס/ת תכנון שבבים (VLSI) יצטרף/תצטרף לצוות ויעסוק/תעסוק בתכנון RTL, פיתוח IP חדשים ושילוב SoC. התפקיד כולל מעורבות עמוקה בחקר ארכיטקטורה, הערכת פרוטוקולים ועבודת תכנון מעשית על פני בלוקים מרובים של שבבים.
- BSc or MSc in Electrical Engineering / Computer Engineering from a leading academic institution
- 3–7 years of hands-on experience in VLSI / ASIC design
- Solid experience in VLSI design (candidates with only FPGA experience will not be considered)
- Familiarity with the RTL-to-GDSII full flow
חולץ מתיאור המשרה · מתעדכן אוטומטית
למי זה מתאים
התפקיד מתאים למהנדסים/ות בעלי/ות 3-7 שנות ניסיון בתכנון VLSI/ASIC, עם תואר ראשון או שני בהנדסת חשמל/מחשבים. הוא אינו מתאים למועמדים/ות עם ניסיון ב-FPGA בלבד.
תיאור המשרה המלא
המשרה המקורית · נשמר לעיוןWe are Hiring: Chip Design Engineer (VLSI)
Location: Israel (Central Region)
Experience Level: Mid-level (3–7 years)
Position Type: Full-time
About the Company
We are an established, stable, and highly successful semiconductor company delivering tens of millions of chips annually to top-tier global customers in the Security, Cloud, and Computing domains.
What makes us unique? Our Israel Design Center is fully self-contained—covering everything from product definition and architecture to design, software, validation, and test. This means you get real ownership over the final silicon, a warm and collaborative culture where your impact is clearly seen, and no late-night calls across conflicting time zones.
The Role
We are looking for an experienced Chip Design Engineer to join our growing team and take a key role in RTL design, new IP development, and SoC integration. In this position, you will be deeply involved in architectural exploration, protocol evaluation, and hands-on design work across multiple chip blocks.
Key Responsibilities
• RTL design and implementation of new IPs.
• SoC integration and design ownership of complex chip subsystems.
• Exploration and evaluation of new protocols and architectural solutions.
• Close collaboration with Architecture, Verification, Validation, Software, and Back-end teams.
• Delivering high-quality, best-in-class RTL that meets performance, power, and area (PPA) goals.
Requirements
• Education: BSc or MSc in Electrical Engineering / Computer Engineering from a leading academic institution.
• Experience: 3–7 years of hands-on experience in VLSI / ASIC design.
• Must-Have: Solid experience in VLSI design (candidates with only FPGA experience will not be considered).
• Advantage: Familiarity with the RTL-to-GDSII full flow.
• Soft Skills: Strong analytical thinking, excellent communication skills, and a great team-player mindset for a multi-disciplinary environment.
שאלות על המשרה
- המשרה לא ציינה שכר. אנחנו מציגים שכר רק כשהמעסיק מפרסם אותו.
- BSc or MSc in Electrical Engineering / Computer Engineering from a leading academic institution, 3–7 years of hands-on experience in VLSI / ASIC design, Solid experience in VLSI design (candidates with only FPGA experience will not be considered)