Frontend VLSI Design And Verification Engineer
פורסם לפני 24 ימים · 0 מועמדים
התפקיד במילים פשוטות
מהנדס/ת תכנון ואימות VLSI Frontend ב-NeoLogic יעצב, יטמיע ויאמת בלוקים ותתי-מערכות דיגיטליים עבור מעבדי שרת AI מהדור הבא. הפעילות היומיומית כוללת תכנון RTL, הגדרת מיקרו-ארכיטקטורה, כתיבה וסקירת מפרטי תכנון, ושיתוף פעולה הדוק עם צוותי ארכיטקטורה ובקאנד. התפקיד כולל גם פיתוח ותחזוקת סביבות אימות, יצירת תוכניות בדיקה, הטמעת סביבות בדיקה וניתוח תוצאות סימולציה.
- Strong background in digital design, including RTL development (e.g., Verilog/SystemVerilog or VHDL) and micro-architecture for complex SoCs or CPU subsystems
- Hands-on experience in functional verification, including testbench development, constrained-random testing, coverage-driven verification, and debugging simulation failures
- Familiarity with industry-standard EDA tools and flows for frontend design and verification (e.g., simulators, lint, CDC, synthesis, and formal verification tools)
- Knowledge of computer architecture concepts such as pipelines, caches, memory subsystems, and interfaces relevant to high-performance AI/server CPUs
- Proficiency in scripting or programming languages (e.g., Python, Perl, shell, or C/C++) to automate verification tasks and improve design workflows
- Experience with AI accelerators, high-speed interfaces, or advanced process nodes
חולץ מתיאור המשרה · מתעדכן אוטומטית
למי זה מתאים
התפקיד מתאים למהנדסים בעלי רקע חזק בתכנון דיגיטלי וניסיון מעשי באימות פונקציונלי, כולל פיתוח סביבות בדיקה וניפוי כשלים. נדרשת היכרות עם כלי EDA סטנדרטיים בתעשייה ועם מושגי ארכיטקטורת מחשב. יתרון לבעלי ניסיון עם מאיצי AI או ממשקים מהירים.
תיאור המשרה המלא
המשרה המקורית · נשמר לעיוןCompany Description NeoLogic develops high-performance AI server CPUs built on its proprietary AI-driven CMOS+ technology. This innovation delivers superior power, performance, and area (PPA) compared to traditional CMOS-based processor designs across all technology nodes. The company focuses on pushing the boundaries of compute efficiency for AI workloads and advanced data-center applications. Team members work in a highly technical, fast-paced environment that values creativity, rigorous engineering, and impact-driven design. NeoLogic offers opportunities to contribute to cutting-edge processor architectures that shape the future of AI computing. Role Description As a Frontend VLSI Design and Verification Engineer at NeoLogic, you will design, implement, and verify digital blocks and subsystems for next-generation AI server CPUs. Day-to-day activities include RTL design, micro-architecture definition, writing and reviewing design specifications, and collaborating closely with architecture and backend teams. You will develop and maintain verification environments, create test plans, implement testbenches, and analyze simulation results to ensure functional correctness and robustness. The role also involves debugging complex design and verification issues, optimizing for PPA, and participating in code reviews and design reviews. This is a full-time, on-site position located in Israel. Qualifications
• Strong background in digital design, including RTL development (e.g., Verilog/SystemVerilog or VHDL) and micro-architecture for complex SoCs or CPU subsystems.
• Hands-on experience in functional verification, including testbench development, constrained-random testing, coverage-driven verification, and debugging simulation failures.
• Familiarity with industry-standard EDA tools and flows for frontend design and verification (e.g., simulators, lint, CDC, synthesis, and formal verification tools).
• Knowledge of computer architecture concepts such as pipelines, caches, memory subsystems, and interfaces relevant to high-performance AI/server CPUs.
• Proficiency in scripting or programming languages (e.g., Python, Perl, shell, or C/C++) to automate verification tasks and improve design workflows.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience.
• Ability to work collaboratively in multidisciplinary teams, communicate technical ideas clearly, and take ownership of tasks from specification to tape-out.
• Experience with AI accelerators, high-speed interfaces, or advanced process nodes is an advantage.
שאלות על המשרה
- המשרה לא ציינה שכר. אנחנו מציגים שכר רק כשהמעסיק מפרסם אותו.
- מהמשרד
- Strong background in digital design, including RTL development (e.g., Verilog/SystemVerilog or VHDL) and micro-architecture for complex SoCs or CPU subsystems, Hands-on experience in functional verification, including testbench development, constrained-random testing, coverage-driven verification, and debugging simulation failures, Familiarity with industry-standard EDA tools and flows for frontend design and verification (e.g., simulators, lint, CDC, synthesis, and formal verification tools), Knowledge of computer architecture concepts such as pipelines, caches, memory subsystems, and interfaces relevant to high-performance AI/server CPUs, Proficiency in scripting or programming languages (e.g., Python, Perl, shell, or C/C++) to automate verification tasks and improve design workflows