Sr. Physical Design Engineer

A leading space technology company is developing next-generation satellite communication solutions based on advanced in-house-designed chipsets.

The company operates at the intersection of satellite systems, semiconductor technology, communications infrastructure, and space-grade engineering, supporting complex missions and next-generation connectivity applications.

This is an opportunity to join a highly technical VLSI engineering environment and take part in the physical implementation of complex SoC, VLSI devices, and test chips, integrating custom designs and third-party IP.

Responsibilities

• Own physical implementation of complex SoC, VLSI devices, and test chips, integrating custom designs and third-party IP.

• Lead block-level timing closure and manufacturing signoff, including power planning and power analysis.

• Work closely with Logic Design / RTL teams to develop timing constraints for block-level and chip-level implementation.

• Execute and optimize the physical design flow, including synthesis, floorplanning, place & route, CTS, parasitic extraction, STA, timing closure, physical verification, and formal verification.

• Support DFT test structure insertion, ATPG, chip-level integration, capture, and simulation.

• Work with third-party IP and library suppliers, EDA tool vendors, and subcontract design service providers to improve scripts, tools, and design flow.

• Use scripting languages such as Tcl, Python, or Perl to automate and improve physical design processes.

Required Qualifications

• B.Sc. in Electrical Engineering, Computer Science, or a related field from a recognized academic institution- must.

• At least 8 years of experience as a Physical Design Engineer - must.

• Strong experience with COT / ASIC physical design flow, including synthesis, floorplanning, P&R, CTS, parasitic extraction, STA, timing closure, physical verification, power analysis, formal verification, DFT / DFM, and ATPG- must.

• Experience with deep sub-micron process technologies, 28nm or below - must.

• Strong understanding of industry-standard design processes for deep sub-micron designs- must.

• Practical experience with scripting languages such as Tcl, Python, or Perl - must.

• Experience with at least one major EDA tool flow, such as Cadence or Synopsys - must.

Job No. 500393