FPGA Verification Engineer
פורסם לפני 14 ימים · 0 מועמדים
התפקיד במילים פשוטות
התפקיד כולל פיתוח והרצה של סביבות אימות (Verification) עבור רכיבי FPGA ומודולים פנימיים תוך שימוש במתודולוגיית SystemVerilog UVM. בנוסף, התפקיד דורש כתיבת תסריטי אוטומציה ב-Python ו-TCL, השתתפות בבדיקות מעבדה ותיעוד תהליכי האימות.
- B.Sc. in Electrical Engineering or Electronics Engineering
- At least 3 years of experience in FPGA Verification
- Proven experience developing verification environments based on UVM and reuse-oriented methodologies
- Experience integrating verification environments and verification components
- Hands-on experience implementing and reporting Functional Coverage
- Familiarity with Assertion-Based Verification (ABV) methodologies
- Experience working with and integrating Verification IPs (VIPs) into verification environments
- Strong knowledge of communication protocols such as AXI, SPI, I²C, Ethernet, and PCIe
- Experience with FPGA design and development processes using VHDL and Verilog
חולץ מתיאור המשרה · מתעדכן אוטומטית
למי זה מתאים
התפקיד מתאים למהנדסי חשמל או אלקטרוניקה בעלי ניסיון של לפחות 3 שנים באימות FPGA ופיתוח סביבות אימות מבוססות UVM. הוא פחות יתאים למי שאין לו ניסיון מעשי מוכח ב-Functional Coverage ובשימוש ב-UVM Scoreboard.
תיאור המשרה המלא
המשרה המקורית · נשמר לעיוןAbout the Role
The Engineering & Systems Division within the Missiles & Space Group is seeking an FPGA Verification Engineer to join a highly skilled and dynamic development team working on advanced multidisciplinary defense systems.
This role offers the opportunity to work on cutting-edge FPGA-based solutions deployed across land, air, naval, and space platforms, while contributing to the verification and validation of complex programmable logic designs.
Key Responsibilities
• Join a small, highly professional development team as part of a multidisciplinary project environment.
• Develop and execute verification environments for FPGA devices and internal modules using Random-Based Verification methodologies.
• Utilize SystemVerilog UVM methodologies throughout the verification lifecycle, including Test Plan definition, Random Constraint development, and Functional Coverage implementation.
• Maintain and enhance existing verification environments developed in Verilog, VHDL, and SystemVerilog.
• Develop automation and support scripts using Python and TCL.
• Participate in laboratory testing and design validation activities.
• Prepare verification and test documentation.
• Collaborate with internal and external stakeholders, contribute to technical specifications, and support system integration activities.
Requirements
• B.Sc. in Electrical Engineering or Electronics Engineering .
• Knowledge of Signal Processing and Control Systems.
• At least 3 years of experience in FPGA Verification.
• Proven experience developing verification environments based on UVM and reuse-oriented methodologies.
• Experience integrating verification environments and verification components.
• Hands-on experience implementing and reporting Functional Coverage.
• Experience working with UVM Scoreboard and UVM Register Model (RGM).
Preferred Qualifications
• Familiarity with Assertion-Based Verification (ABV) methodologies.
• Experience working with and integrating Verification IPs (VIPs) into verification environments.
• Strong knowledge of communication protocols such as AXI, SPI, I²C, Ethernet, and PCIe.
• Experience with FPGA design and development processes using VHDL and Verilog.
Why Join Us?
Our FPGA Logic Design & Signal Processing group consists of highly experienced engineers with deep technological expertise and a passion for innovation.
The technologies developed by our team are integrated into advanced defense systems operating across land, air, sea, and space domains, providing a unique opportunity to work on complex, mission-critical solutions at the forefront of technological advancement.
If you are passionate about FPGA verification, advanced digital design methodologies, and working on challenging multidisciplinary systems, we would love to hear from you.
שאלות על המשרה
- המשרה לא ציינה שכר. אנחנו מציגים שכר רק כשהמעסיק מפרסם אותו.
- B.Sc. in Electrical Engineering or Electronics Engineering, At least 3 years of experience in FPGA Verification, Proven experience developing verification environments based on UVM and reuse-oriented methodologies, Experience integrating verification environments and verification components, Hands-on experience implementing and reporting Functional Coverage