Logic Digital Verification Engineer
פורסם 15 ביולי · 0 מועמדים
התפקיד במילים פשוטות
תפקיד זה כולל הובלה ובנייה של סביבות אימות תכנון (Verification) מורכבות עבור מוצר הליבה של החברה. ביום-יום, המהנדס יגדיר וייישם פתרונות אימות ב-SV/UVM ברמת הבלוק וברמת ה-SoC, תוך עבודה צמודה עם צוותי האנלוג, התוכנה והסיסטם.
- B.Sc. in Electrical Engineering, Computer Engineering, or relevant engineering department graduate with high scores, or equivalent experience
- 2+ years in design verification with strong SV/UVM proficiency
- SystemVerilog (SV)
- UVM methodology
- Understanding of digital ASIC design flows and SoC development methodologies
- Knowledge in Low Power techniques and UPF standard
- Knowledge in Mix signals SoCs
- Experience with SW/HW Co-development
חולץ מתיאור המשרה · מתעדכן אוטומטית
למי זה מתאים
התפקיד מתאים למהנדסי חשמל או מחשבים עם שנתיים ומעלה של ניסיון באימות תכנון ואינטגרציה של SV/UVM, או לבוגרים מצטיינים עם ידע נרחב ב-RTL. הוא פחות מתאים למי שאינו בעל רקע הנדסי מתאים או ללא היכרות עם זרמי פיתוח ASIC.
תיאור המשרה המלא
המשרה המקורית · נשמר לעיוןWiliot was founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the world’s largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products. Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo. Wiliot is looking for a talented and experienced engineer to take part in the verification efforts for the company’s core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path. Responsibilities: • Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration. • Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements: • Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience. • 2+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered) • Self-motivated, ability to work, lead and drive tasks to completion. • Great interpersonal skills. • Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control. Advantages • Knowledge in Low Power techniques and UPF standard. • Knowledge in Mix signals SoCs. • Experience with SW/HW Co-development #LI-Hybrid
שאלות על המשרה
- המשרה לא ציינה שכר. אנחנו מציגים שכר רק כשהמעסיק מפרסם אותו.
- היברידי
- B.Sc. in Electrical Engineering, Computer Engineering, or relevant engineering department graduate with high scores, or equivalent experience, 2+ years in design verification with strong SV/UVM proficiency, SystemVerilog (SV), UVM methodology, Understanding of digital ASIC design flows and SoC development methodologies