Senior AI STA Engineer, Sub-chip
פורסם לפני 9 ימים · 0 מועמדים
התפקיד במילים פשוטות
התפקיד כולל ביצוע ניתוח זמנים סטטי (STA) מתקדם ושימוש בכלי AI לטובת אופטימיזציה וניתוח נתונים ב-STA וב-PnR עבור שבבים מורכבים. העבודה היומיומית כוללת הרצה ובנייה של כלי STA, שימוש ב-PrimeTime, איתור סיכוני התכנסות וסגירת זמנים משלב המודל ועד ה-signoff, תוך עבודה מול צוותי physical design, RTL ו-DFT.
- B.SC./ M.SC. in Electrical Engineering
- At least 5+ years of hands-on STA experience
- PrimeTime
- Signoff methodologies and timing closure
- Collaboration and cross-team alignment with physical design, RTL, and DFT teams
- Agentic Frameworks
- AI prompting experience
- Experience in Linux environments
- TCL, Python, shell scripting abilities
- Experience with data collection and analysis
חולץ מתיאור המשרה · מתעדכן אוטומטית
למי זה מתאים
התפקיד מתאים למהנדסי חשמל בעלי ניסיון מעשי של לפחות 5 שנים ב-STA ומתודולוגיות signoff, עם רקע או רצון ללמוד כלי AI. הוא פחות מתאים לחסרי ניסיון משמעותי ב-STA או למי שאינם בעלי תואר בהנדסת חשמל.
תיאור המשרה המלא
המשרה המקורית · נשמר לעיוןJob Requisition ID JR2015231
Job Category Engineering
Time Type Full time
NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What You'll Be Doing
• Perform advanced AI Static Timing Analysis (STA) for complex chiplet and full chip level.
• AI use for timing optimization and data analysis in STA and PnR.
• Running and build STA tools for anlyaze and debug timing.
• Use traditional STA tools like Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
• Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
• Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.
What We Need To See
• B.SC./ M.SC. in Electrical Engineering.
• At least 5+ years of hands-on STA experience.
• Experience in Prime Time and signoff methodologies.
• A great teammate who thrives in a collaborative environment.
• AI tools orientation or alternatively a desire to learn.
Ways To Stand Out From The Crowd
• Agentic Frameworks.
• AI prompting experience.
• Experience in Linux environments.
• TCL, Python, shell scripting abilities.
• Experience with data collection and analysis.
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!
שאלות על המשרה
- המשרה לא ציינה שכר. אנחנו מציגים שכר רק כשהמעסיק מפרסם אותו.
- B.SC./ M.SC. in Electrical Engineering, At least 5+ years of hands-on STA experience, PrimeTime, Signoff methodologies and timing closure, Collaboration and cross-team alignment with physical design, RTL, and DFT teams