Formal verification engineer

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Description

About the Business Unit:

Here at Ceva, we are developing state-of-the-art DSP, AI processors and HW accelerator ASIC projects in AI, Vision, Wireless, and Base-stations areas.

About The Role

In this role, you will join our Formal Verification team, executing full verification cycle from architectural definition and FV strategy definition to full execution and final sign-off, utilizing advanced Formal Verification methodologies and tools.

This role allows for independent work, impactful input, and substantial contributions to the VLSI department’s verification tasks

Responsibilities

Develop Formal Testbenches and Properties - Write and maintain SystemVerilog Assertions to formally verify RTL designs using industry-standard formal tools.

Collaborating with Design and Verification Teams

Contribute to Verification Planning and Coverage

Define formal verification plans, track progress, and contribute to achieving verification completeness.

Requirements

• Bachelor’s degree in electrical engineering from a leading university.

• Proficiency in System Verilog is essential.

• A proactive, self-driven individual with problem-solving and complex analysis capabilities.

• Capable of delivering results in a dynamic, agile environment, both independently and organization-wide

Advantages

• Practical experience with Jasper is beneficial; familiarity with SV-UVM, Python, and Tcl is advantageous.

• Experience in Formal Verification or Dynamic Verification