FPGA Team Lead

An industry-leading technology pioneer engineering next-generation communication fabrics and high-performance computation platforms.

The enterprise specializes in custom, ultra-low-latency electronic architectures built to handle massive data throughput and complex mathematical calculations in real time.

Operating at the intersection of high-frequency hardware acceleration and complex network routing, the organization provides an elite technical ecosystem for engineering professionals.

The primary R&D facility is located in the Central region of Israel, operating under a professional hybrid model that supports one day of remote work per week.

Position Overview-

• Principal / Lead FPGA Architect serving as the ultimate technical authority for the design, architecture, and deployment of complex, high-throughput logic systems.

• Leading the system-level design strategy and architectural trade-offs, partnering directly with cross-functional Systems, RF, Hardware, and Embedded Software engineering cells.

• Mapping, designing, and deploying advanced digital signal processing (DSP) algorithms including high-performance filtering, multi-channel processing, and channelization natively into silicon fabrics.

• Directing high-speed data path integration, optimizing architectures for strict low-latency execution, minimal power consumption, and maximum resource utilization.

• Owning the comprehensive silicon development lifecycle from initial requirements compilation through heavy simulation and physical synthesis to final hardware validation.

• Serving as an engineering mentor, defining corporate Best Practices, coding standards, and verification methodologies across the logic department.

• Core Domain & Ecosystem- FPGA Architecture, VHDL / Verilog / System Verilog, Digital Signal Processing (DSP), High-Speed SerDes & Transceivers, Clock Tree & Clock Distribution Architectures, Signal Integrity, Board Bring-up, System Integration, and Lab Instrumentation.

Requirements-

• Academic Background: B.Sc. or M.Sc. in Electrical Engineering, Electronic Engineering, or an equivalent exact science discipline from a recognized academic institution – Mandatory

• 8+ years of deep, hands-on professional experience in complex FPGA design, synthesis, and logic routing – Mandatory

• Expert-level theoretical and practical mastery of Digital Signal Processing (DSP) implementations within hardware fabrics – Mandatory

• Advanced programming fluency in standard Hardware Description Languages (VHDL, Verilog, or SystemVerilog) – Mandatory

• First-principles technical comprehension of SerDes architectures, multi-gigabit transceivers, and complex clocking infrastructures – Mandatory

• Production-proven experience leading high-speed link bring-up, lab debugging, and signal integrity validation utilizing advanced laboratory test equipment (e.g., oscilloscopes, BERTs) – Mandatory

• Strong systemic vision with a demonstrated track record of driving multi-disciplinary hardware-software integration loops – Mandatory

• Full professional fluency in technical English (both verbal and written communication) – Mandatory