FPGA Verification Engineer
פורסם אתמול · 0 מועמדים
- B.Sc. in Electrical / Electronics Engineering
- 3+ years of hands-on experience in FPGA/ASIC verification
- UVM
- SystemVerilog
- Environment setup and detailed coverage reporting
- Assertion-Based Verification (ABV)
- Familiarity with VIPs and communication protocols (PCIe, Ethernet, I2C, SPI, AXI)
- RTL Design background
חולץ מתיאור המשרה · מתעדכן אוטומטית
תיאור המשרה המלא
המשרה המקורית · נשמר לעיוןWe're Hiring! FPGA Verification Engineer | Leading Defense Company
Are you an experienced FPGA Verification Engineer looking to work on cutting-edge systems that truly matter? Join our elite engineering team in Central Israel and take a lead role in building advanced verification environments for next-generation defense technologies.
What You’ll Do-
• Architect & Execute: Build and run advanced, scalable verification environments using SystemVerilog & UVM.
• End-to-End Testing: Develop dynamic test plans, complex testbenches, and execute full-scale simulations.
• Deep-Dive Verification: Drive Functional Coverage, Constraint-Random testing, UVM scoreboards, and register model implementation.
• Legacy Support: Support and maintain existing legacy environments in Verilog/VHDL.
• Automation: Write efficient scripts in Python and TCL to streamline workflow automation.
What We’re Looking For-
• Education: B.Sc. in Electrical / Electronics Engineering - Mandatory.
• Experience: 3+ years of hands-on experience in FPGA/ASIC verification.
• Core Tech: Proven experience with UVM & SystemVerilog.
• Environment Integration: Strong background in environment setup and detailed coverage reporting.
• Scripting: Solid hands-on capabilities in Python and TCL.
Nice to Have-
• Experience with Assertion-Based Verification (ABV).
• Familiarity with VIPs and key communication protocols (PCIe, Ethernet, I2C, SPI, AXI).
• Prior background in RTL Design (Verilog/VHDL).
שאלות על המשרה
- המשרה לא ציינה שכר. אנחנו מציגים שכר רק כשהמעסיק מפרסם אותו.
- B.Sc. in Electrical / Electronics Engineering, 3+ years of hands-on experience in FPGA/ASIC verification, UVM, SystemVerilog, Environment setup and detailed coverage reporting