Junior Digital Verification Engineer

Samsung Israel Research Center (SIRC) is shaping the world of tomorrow, today. Focusing beyond the horizon and pushing exciting developments in many key areas of technology. Samsung is creating a new era of continuous innovation, bringing value and contribution to society and creating a workplace where our employees can enjoy making the most of their talent, creativity and passion. Samsung R&D Center is looking for Junior Digital Verification Engineer to join our Memory team! Join the cutting-edge team at Samsung R&D Center as we embark on shaping the future of technology today. The Group The R&D center is part of Samsung’s world-leading Flash memory division, which is responsible for developing and manufacturing SSD, eMMC/UFS, and emerging memory products. The center conducts research and development of signal processing algorithms and system architecture for Samsung’s next generation platforms. The center includes experienced researchers in the fields of machine learning, signal processing, error correction codes, encryption and data security. We offer the candidates a unique opportunity for personal development. · Work with innovative and top caliber memory experts in a collegial and fun environment. · Work on challenging and innovative solutions for cutting-edge hardware of Samsung world-class memory products. · Work in a dynamic team that provides continuous opportunities for learning and growth. What will you do? · Join the full verification cycle for complex digital designs, from initial verification planning and test execution through to rigorous coverage closure. · Implement SystemVerilog Assertions (SVA) and drive deep code coverage analysis · Debug complex tests and trace analysis alongside design engineers to deliver functionally pristine blocks and finalize regressions. · Collaborate closely with design and algorithm engineers · Continuously expand your technical expertise by tackling increasingly complex verification challenges in a highly collaborative environment

Requirements: · BSc in Electrical Engineering or Computer Engineering from leading university. · High ambition, passion for solving complex hardware challenges, and a proven motivation to learn and adapt to new technologies. Advantages · Scripting skills in Python and experience with Linux/Unix environments. · Hands-on experience in SystemVerilog and UVM · Experience with Cadence tools such as Xcelium, vManager, and Indago.