Senior Design Verification Engineer

Senior RTL Verification Engineer – RISC-V Application Processor

Lead the verification of complex subsystems and architectural features within a next-generation, high-performance RISC-V Application Processor, taking ownership from architecture and specification through tape-out. The role combines deep technical verification expertise with system-level understanding, working closely with architecture, RTL design, modeling, software, validation, and implementation teams to ensure functional correctness and first-pass silicon success while meeting demanding Performance, Power and Area (PPA) targets.

You will define and drive verification strategies, test plans, coverage models and closure methodologies, as well as architect and develop scalable SystemVerilog/UVM verification environments. Responsibilities include constrained-random and directed testing, assertions and SVA, functional coverage, regression management, RTL debug and root-cause analysis of complex hardware and verification issues. The role also involves identifying verification risks, influencing architecture and design decisions, and improving verification methodologies and productivity across projects.

The ideal candidate brings 5+ years of RTL/ASIC verification experience, strong knowledge of CPU/SoC architecture and microarchitecture, and hands-on expertise in SystemVerilog, UVM, SVA and RTL debugging. Experience with RISC-V, MMU and virtual memory, cache and memory hierarchy, cache coherency, interconnects or high-performance CPU cores is highly relevant. Strong C/C++ skills and familiarity with Python or other scripting languages are advantageous.

This is a senior technical role requiring independent ownership of complex verification domains, strong analytical and debugging capabilities, cross-functional collaboration, and the ability to lead technical initiatives and mentor junior engineers.