Senior Design Verification Engineer

An international semiconductor company is looking for a Senior Design Verification Engineer to join its R&D team in Ramat Gan.

This is a hands-on senior role with ownership across verification architecture, methodology, automation and sign-off for complex ASIC/SoC designs.

What you’ll work on

• Build and optimise scalable SystemVerilog/UVM verification environments

• Own verification at block and subsystem level

• Constrained-random verification, SVA and formal verification

• Functional/code coverage and verification closure

• Python automation, regression flows and CI/CD

• Integration of C/C++ reference models

• Work closely with RTL designers and chip architects

What we’re looking for

• Extensive ASIC/SoC Design Verification experience

• Strong SystemVerilog and UVM

• Strong Python/scripting and automation skills

• Experience with complex SoCs and verification sign-off

• Experience with Questa and/or Xcelium

• C/C++ knowledge is advantageous

• Communications SoC experience is a plus

If you’re a senior Design Verification / ASIC Verification / SoC Verification Engineer in Israel looking for a role with significant technical ownership, apply for a confidential discussion or contact Steph Hutchinson.