Senior FPGA Engineer
פורסם אתמול · 0 מועמדים
התפקיד במילים פשוטות
מהנדס/ת FPGA בכיר/ה שיוביל/תוביל תהליכי ארכיטקטורה, פיתוח RTL ב-Verilog, סימולציות ואימות עבור מערכות מבוססות AMD Versal. התפקיד כולל עבודה מקצה לקצה בכלי Vivado, סגירת תזמונים (timing closure), ואינטגרציה מעבדתית הכוללת בדיקות board bring-up בשיתוף צוותי חומרה ותוכנה. בנוסף, נדרשת הובלה טכנית והתמודדות עם ממשקים מהירים כגון PCIe, Ethernet ו-DDR.
- B.Sc. in Electrical Engineering, Electronics Engineering, Computer Engineering, or an equivalent field
- At least 6 years of hands-on FPGA design experience in a product-development environment
- Deep proficiency in synthesizable Verilog RTL design
- AMD Versal adaptive SoCs
- High-speed interfaces: multi-gigabit transceivers (GTY, GTM), PCIe, Ethernet, DDR3/DDR4/DDR5
- Practical experience using AI-assisted tools across FPGA development lifecycle
- Embedded or SoC development experience with Versal or Zynq (ARM, AXI, PetaLinux, bare-metal drivers)
- Tcl scripting and FPGA build-flow automation
- Vitis
- Network-testing equipment and communication-system testing environments
חולץ מתיאור המשרה · מתעדכן אוטומטית
למי זה מתאים
מתאים לבעלי תואר רלוונטי בהנדסה עם לפחות 6 שנות ניסיון מעשי בפיתוח FPGA, שליטה ב-Verilog, וניסיון מוכח ב-AMD Versal ובסביבת Vivado ומעבדה. פחות מתאים למהנדסים מתחילים או למי שמחפש תפקיד ממוקד תוכנה בלבד ללא נגיעה במעבדה ובחומרה.
תיאור המשרה המלא
המשרה המקורית · נשמר לעיוןSenior FPGA Engineer
📍 Location: Raanana, Israel
🕒 Employment type: Full-time
The Role
We are looking for a Senior FPGA Engineer to join our FPGA team and take a leading technical role in the architecture, design, implementation, and verification of complex FPGA-based products.
This is a hands-on position with end-to-end technical ownership, from architecture and RTL development through simulation, FPGA implementation, system integration, and board bring-up.
You will work closely with hardware, software, and system engineers, influence key architectural decisions, and see your designs deployed in real products in the field.
Responsibilities
• Design and implement complex digital logic in Verilog, from specifications and microarchitecture through RTL development and implementation in a working device.
• Develop solutions based on AMD Versal adaptive SoCs, including the selection, configuration, and integration of IP cores and hard blocks.
• Own the complete Vivado implementation flow, including synthesis, constraints, place and route, timing closure, resource optimization, and on-chip debugging using ILA.
• Develop and maintain simulation environments and testbenches and perform functional verification using ModelSim and Questa.
• Review hardware schematics, define FPGA pinouts and interfaces, and support board bring-up, system integration, and hardware debugging alongside the hardware team.
• Write and review technical documentation, including design specifications, interface definitions, verification plans, and test reports.
• Investigate and resolve system-level issues in the lab using oscilloscopes, logic analyzers, and protocol analyzers.
• Collaborate with multidisciplinary hardware, software, and system teams throughout the product development lifecycle.
• Provide technical leadership through design reviews, problem-solving, and guidance to other team members.
Requirements: Must Have
• B.Sc. in Electrical Engineering, Electronics Engineering, Computer Engineering, or an equivalent field.
• At least 6 years of hands-on FPGA design experience in a product-development environment.
• Deep proficiency in synthesizable Verilog RTL design.
• Proven experience developing with AMD Versal adaptive SoCs.
• Hands-on experience with high-speed interfaces and technologies, including:
• Multi-gigabit transceivers, such as GTY and GTM
• PCI Express
• Ethernet
• DDR3, DDR4, and DDR5
• Strong, proven experience with the Vivado toolchain, including timing constraints, timing analysis, and timing closure.
• Solid verification experience using ModelSim and/or Questa, including testbench development, simulation, waveform analysis, and debugging.
• Ability to read and review hardware schematics, define FPGA interfaces and pinouts, and work closely with board designers.
• Practical laboratory experience with board bring-up, integration, and hardware debugging.
• Strong analytical, debugging, and problem-solving skills.
• Ability to work independently, take technical ownership, and collaborate effectively across hardware, software, and system teams.
• Good written and spoken English.
Advantages
• Practical experience using AI-assisted tools throughout the FPGA development lifecycle,
including:
• System architecture and microarchitecture definition
• RTL development, analysis, and code review
• Testbench development and verification planning
• Simulation, waveform analysis, and debugging
• Timing-closure analysis and implementation-flow optimization
• Technical documentation
• Scripting and workflow automation
• Ability to use AI tools effectively while independently reviewing and validating generated outputs for functional correctness, synthesizability, timing implications, and compliance with design requirements.
• Embedded or SoC development experience with Versal or Zynq, including ARM processing systems, AXI infrastructure, PetaLinux, and bare-metal software and drivers.
• Experience with Tcl scripting and FPGA build-flow automation.
• Experience using Vitis.
• Familiarity with data-communication protocols and systems, particularly PON and Ethernet.
• Experience with network-testing equipment and communication-system testing environments.
Why Join Us?
• Take technical ownership of challenging FPGA designs from architecture through deployment.
• Work with advanced AMD Versal technologies and high-speed communication interfaces.
• Collaborate directly with multidisciplinary engineering teams.
• Develop products that move beyond simulation and operate in real systems in the field.
How to Apply
Send their CV to jobs@tracespan.com.
שאלות על המשרה
- המשרה לא ציינה שכר. אנחנו מציגים שכר רק כשהמעסיק מפרסם אותו.
- B.Sc. in Electrical Engineering, Electronics Engineering, Computer Engineering, or an equivalent field, At least 6 years of hands-on FPGA design experience in a product-development environment, Deep proficiency in synthesizable Verilog RTL design, AMD Versal adaptive SoCs, High-speed interfaces: multi-gigabit transceivers (GTY, GTM), PCIe, Ethernet, DDR3/DDR4/DDR5