התפקיד במילים פשוטות
התפקיד כולל תכנון ופיתוח סביבות אימות (Verification) בשיטת UVM ו-SystemVerilog עבור פרויקטי FPGA ו-ASIC, החל מרמת הבלוק ועד לרמת השבב המלא. העבודה כוללת דיבאג של RTL מרמת הבלוק ועד לרמת המערכת, כתיבת סקריפטים, ושימוש בכלי סימולציה. כמו כן, התפקיד דורש עבודה צמודה מול צוותי פיתוח FPGA, מהנדסי מערכת, ארכיטקטורה ואלגוריתמים.
- 5+ years of experience in Verification, from Test Plan definition through Coverage
- Hands-on experience with UVM methodology and SystemVerilog
- Experience developing Verification environments for FPGA / ASIC at both block and full-chip levels
- Experience with RTL debugging from block level to system level
- Experience writing scripts in Python, TCL, Bash / Csh
- Questa Simulator
- B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science
חולץ מתיאור המשרה · מתעדכן אוטומטית
למי זה מתאים
המשרה מתאימה למהנדסי וריפיקציה מנוסים עם לפחות 5 שנות ניסיון מעשי ב-UVM, SystemVerilog וכתיבת סקריפטים בלינוקס. התפקיד פחות מתאים לבוגרים טריים או למי שמחפש עבודה מרחוק, כיוון שמדובר במשרה מלאה באתר בחולון.
תיאור המשרה המלא
המשרה המקורית · נשמר לעיוןabra professional services is seeking a Verification Engineer . We are looking for a skilled Verification Engineer to join a professional and dynamic team and take part in advanced, diverse technology projects in the fields of FPGA Verification, signal processing, controllers, and more. This role requires extensive experience in Verification, UVM methodology, SystemVerilog, FPGA / ASIC verification environments, RTL debugging, simulation tools, scripting, and working closely with FPGA development, system, architecture, and algorithm teams. A full-time on-site position based in Holon, Israel. Key Responsibilities: • Develop verification environments using UVM methodology for FPGA verification across various projects. • Work on verification projects involving signal processing, controllers, and additional advanced technologies. • Define, architect, and develop verification environments from block-level to full-chip level. • Work closely with FPGA development teams, system engineers, architecture teams, and algorithm engineers. • Support RTL debugging from block level to system level.
Requirements: Professional requirements: • B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science - an advantage. • 5+ years of experience in Verification, from Test Plan definition through Coverage - mandatory. • Hands-on experience with UVM methodology and SystemVerilog - mandatory. • Experience developing Verification environments for FPGA / ASIC at both block and full-chip levels - mandatory. • Experience with RTL debugging from block level to system level - mandatory. • Experience working with simulation tools; Questa Simulator is an advantage • Experience writing scripts in Python, TCL, Bash / Csh - mandatory. • Experience working in a Linux environment - mandatory. • Experience working with FPGA, architecture, system, and algorithm teams. • Very good technical English. Personality requirements: • Strong analytical and problem-solving skills. • Ability to work independently and as part of a team. • Ability to work in a multidisciplinary environment.
שאלות על המשרה
- המשרה לא ציינה שכר. אנחנו מציגים שכר רק כשהמעסיק מפרסם אותו.
- מהמשרד
- 5+ years of experience in Verification, from Test Plan definition through Coverage, Hands-on experience with UVM methodology and SystemVerilog, Experience developing Verification environments for FPGA / ASIC at both block and full-chip levels, Experience with RTL debugging from block level to system level, Experience writing scripts in Python, TCL, Bash / Csh