Verification Engineer

An innovative early-stage Deep-Tech Semiconductor startup operating in stealth mode, building groundbreaking silicon architecture and hardware technology from the ground up (0-to-1).

Backed by premier investors and led by a distinguished team of seasoned chip-design veterans, the company is pioneering novel approaches at the intersection of Silicon, Analog circuits, and Power Electronics.

Assembling its foundational core engineering team, the organization offers a rare ground-floor opportunity to shape the architectural roadmap, take complete ownership of end-to-end chip development, and drive meaningful impact in an elite R&D environment.

The company is located in the Sharon region and operates on a hybrid model with two days working from home.

Role Description-

• Serving as a Lead / Senior Chip Verification Engineer, taking end-to-end ownership of the complete verification lifecycle for advanced, next-generation silicon architectures.

• Architecting, developing, maintaining, and scaling cutting-edge verification environments and testbenches using SystemVerilog and UVM.

• Driving verification planning from specification review through to full regression execution, hands-on debugging, and Coverage Closure.

• Implementing Assertion-Based Verification (ABV) using SVA to identify complex architectural defects and streamline debug flows.

• Creating sophisticated Constrained-Random and Directed Test suites, defining and tracking comprehensive Functional Coverage and Code Coverage metrics.

• Building automated regression suites, simulation log parsers, and tool workflows using Python on Linux.

• Collaborating closely with RTL Designers and System Architects to review specifications, debug RTL/Testbench failures, pinpoint root causes, and ensure silicon tape-out quality.

Requirements-

• Bachelor’s Degree (B.Sc.) in Electrical Engineering, Computer Engineering, or a related technical discipline – Mandatory

• Significant hands-on experience in ASIC / Chip Verification across full silicon design lifecycles – Mandatory

• Deep expertise in building and maintaining testbenches using SystemVerilog and UVM – Mandatory

• Proven track record in defining and achieving Functional and Code Coverage closure – Mandatory

• Hands-on proficiency with Assertion-Based Verification (SVA) – Mandatory

• Strong scripting and automation skills in Python within a Linux environment – Mandatory

• Strong lab debugging skills and experience collaborating deeply with RTL Design teams – Mandatory