VLSI Verification Engineer

A high-growth, stealth-mode AI startup developing innovative artificial intelligence technologies tailored for the semiconductor and chip design industries.

The company was founded by a successful serial entrepreneur with a proven track record of major tech exits and is backed by significant funding alongside a elite team originating from leading semiconductor and AI companies.

Operating in rapid expansion, the company employs over a hundred professionals across two central R&D hubs designed for employee convenience located in Tel Aviv and adjacent to train stations and operate on a hybrid work model with 1 day WFH per week.

Role Description-

• Planning and leading end-to-end validation and verification processes for complex ASIC/SoC designs.

• Building, maintaining, and operating a complete verification environment based on System Verilog and UVM.

• Partnering closely with System Architects, RTL engineers, and Validation teams to debug complex hardware issues.

• Ensuring the quality, resilience, and performance of advanced hardware architectures and silicon components.

Requirements-

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field – Mandatory

• 5 years of hands-on experience in ASIC/SoC verification – Mandatory

• Strong proficiency in SystemVerilog, UVM, and constrained-random verification methodologies – Mandatory

• Deep understanding of digital design, RTL coding (Verilog/VHDL), and simulation flows – Mandatory

• Proven track record in debugging complex hardware/software interactions – Mandatory

• Hands-on experience with industry-standard EDA tools (Synopsys, Cadence, or Siemens/Mentor) – Mandatory

• Excellent analytical, communication, and teamwork skills – Mandatory